The disclosure relates generally to a semiconductor device, and more particularly, to a method for fabricating patterns on a wafer through an exposure process.
A photolithography process is performed to integrate a semiconductor device on a wafer. A photoresist pattern is formed by transferring a layout of a circuit pattern formed on a photomask onto a photoresist layer on the wafer through an exposure process, and a wafer pattern according to the layout of the designed circuit pattern is formed by a patterning process including an etch process using the photoresist pattern as an etch mask.
FIG. 1 illustrates a photomask used in the photolithography process. Referring to FIG. 1, a photomask 10 is fabricated in a rectangular or tetragonal shape and is provided with a mask field region 11 as a region to be exposed. Die regions 13 are disposed within the mask field region 11. The die regions 13 are disposed with mask patterns according to the layout of designed circuit patterns. A frame region 15 is disposed as a light shielding region around the field region 11. Since the mask field region 11 disposed with the die regions 13 is of a rectangular or tetragonal shape, an exposure field region 30 exposed on a photoresist layer 23 on a wafer 21 upon a single exposure shot comes to have a rectangular or tetragonal shape according to the shape of the mask field region 11, as illustrated in FIG. 2.
Since the wafer 21 is formed in a circular shape, an entire mask field region 11 may be fully transferred to the exposure field region 30 in the middle of the wafer 21 by the exposure shot in a full field region 31 placed in the middle of the wafer 21. On the other hand, the entire mask field region 11 is not fully transferred at a peripheral edge portion of the wafer, but is partially transferred by the exposure shot in a partial field region 33 placed at the peripheral edge portion of the wafer 21. Since the mask field region 11 cannot be fully pattern-transferred in this partial field region 33, the exposure shot on this partial field region 33 is not performed and the device integration in the wafer 21 is limited to the full field region 31 or the middle part of the wafer 21. Since an increase in yield of the number of devices per wafer 21 can be expected when the exposure pattern transfer is performed in the partial field region 33, there has been studied a method for realizing the pattern transfer on the partial field region 33 by exposure.
However, when performing the pattern transfer by processing the exposure shot to the partial field region 33, wafer pattern defects are generated in the partial field region 33 and poor patterns due to these pattern defects can function as particles in the subsequent processes, which are factors causing other defects on the entire wafer 21. Observation shows that this pattern defect results from the exposure defect caused upon the exposure on the partial field region 33. For example, when performing the exposure on this partial field region 33 in a process for forming a storage node of a capacitor of a semiconductor device such as a DRAM memory device, it can be seen that defects and faults are generated in the storage nodes 61 as illustrated in FIG. 3.
Referring to FIG. 3, it can be experimentally confirmed that a defect 63 of loss of the storage node 61, a defect 65 of downsizing of the storage node 61, a defect 67 of connection of adjacent storage nodes 61 or other defects are generated when transferring a photomask for forming the storage node 61 on the partial field region 33 on the wafer 21 by the exposure. Further, it has been confirmed that a defect of loss of an insulation layer 51 may occur in a peripheral region 43 around a cell region 41 in which the storage nodes 61 are formed. To ensure more capacitance of the capacitor of the DRAM device in a limited area, the storage node 61 is formed in a pillar shape, such as a circular pillar and a cylindrical pillar, electrically connected to a transistor device. The storage node 61 is formed in a pillar shape having a very large height as compared to a bottom area to increase an effective area of a dielectric layer, and thus a minute pattern defect generated in the exposure process can result in a serious defect in the shape of the storage node 61.
As described above, since the pattern transfer by the exposure on the partial field region 33 has many defect factors including the storage node defects 63, 65, 67, there has been desired a development of a method of integrating a semiconductor device in the partial field region 33 by transferring patterns with generation of the pattern defects being restricted in the partial field region 33.